(1) A PDK/CAD/IP infrastructure is essential to company's long term competency. It should be a sincere part of company's roadmap and strategy. There is not a successful electronics design company without a clear, solid, quality and consistent PDK/EDA/IP infrastructure in place.
(2) Company gains competence by avoiding mistakes and producing NEEDED, VALUE and QUALITY products in time for customers. Successful companies avoid and learned from previous or other company's mistakes. While ordinary companies consistently make mistakes! This also true for all nations, political parties and individuals.
(3) A successful product design is a result of excellent TEAM executions and GROUP effort. This is particularly true for fast track and high risk product design. Not any single person or group can claim the ownership for the success. It is to every team members' best interest to foster a fair, encouraging, innovative, and rewarding corporate culture.
(4) In today's global environment, most parties companies dealing with are smart and knowledgeable. High quality products have their market segment. Value products also have their market segment. However, less and less market segments are for poor electronics. Companies need to push quality, valuable and affordable products as fast as company can. If there are major defects or issues in final products, sooner or later customers will find out and companies will be on Newspaper front pages!
(5) It is always better to catch all errors at early stage than late in design and product cycle. It is always cost more to correct design mistakes at very last product stage. Products recalls even damage a company's corporate image.
(6) If a failure mode is already reported in design or test, then a check for that failure mode should be incorporated into PDK/CAD or design/system validation. Learning by failure is a costly and sometime not necessary process.
(7) The Quality of the final product is as good as your initial design goal, design process and its verification. It is almost impossible to design a complete high speed and high performance SOC using an obsolete EDA system. This is just like you can not use a design system for motorcycle to design a space shuttle. That is going to be a design disaster!
(8) Bad or incorrect simulation model leads
fail chip or un-necessary failure debugging. Wrong or incorrect design
specification leads to product mis-function. Wrong or misleading market
prediction lead to complete waste of development resource and
other opportunity cost.
(9) Quality PDK deck can catch
layout related mistakes. Carefully review DRC/ERC and LVS result
are essential for first PG success. Also using automation can help
human to do more, however also need to apply common sense in all
situation. Blindly trust
simulation or verification without double checking is dangerous to
final qualification of products.
|What is a PDK||A Process Design Kit
(PDK) is a process
specific bundled elements to work with the Cadence Custom IC tools.
Design and layout engineers use PDK elements to design and
analog mixed/signal integrated circuits.
A PDK includes Cadence process technology file, PV rule files (LVS, DRC, ERC), Parasitic Extraction (RCX/PEX) and Spice Models, device symbols, component CDF, Skill callbacks, Pcells, etc. Everything you need to do IC designs.
|Physical Verification||All tools or software to do DRC, ERC, LVS, and PEX/RCX check are called physical verification..|
|Functional Verification||Functional verification is the task of verifying the logic design conforms to design specification|
Use of various types of logic and mathematical methods to verify the correctness of IC logic or system interactions.In other words, it attempts to prove or verify that certain requirements (also expressed formally) are met, or that certain undesired behaviors (such as deadlock) cannot occur.
Equivalence checking is the most common formal verification method, which is used to compare the design that is being created against a design that is already proved accurate.
|Static Timing Analysis||Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation.|
|Hold time violation||A hold time violation,
when an input signal change too
the clock's active transition
|Setup time violation||A setup time violation, when a signal arrives too late, and misses the time when it should advance|
Scan chains are a technique used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. A special signal called scan enable is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register, one input pin provides the data to this chain, and one output pin is connected to the output of the chain. Then using the chip's clock signal, an arbitrary pattern can be entered into the chain of flips flops, and/or the state of every flip flop can be read out.
|Tcl||Tool command language (Tcl) for scripting or GUI|
|Standard VCD||VCD files contain simulation events represented using 4 states: 0, 1, X and Z. This format is excellent for capturing vectors. Ability to write out multiple VCD files.|
|Extended VCD||Based on the Standard VCD files by providing additional information in an 8-state format.|
|Code Coverage||Quickly identify holes in the testing process and reduce simulation times. Ability to merge results of multiple option coverage runs and remove or add files from the coverage statistics|
Finite State Machine (FSM).
An electronic circuit that has a predictable or finite state that is based on a combination of the circuit's previous state and the circuit's current set of inputs.
|LSF||Load Sharing Facility (LSF)|
|Slack Time||The slack associated with each connection is the difference between the required time and the arrival time. A positive slack S at a node implies that the arrival time at that node may be increased by S without affecting the overall delay of the circuit. Conversely, negative slack implies that a path is too slow, and the path must be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.|
|STA is a method of computing the expected timing of a digital circuit without requiring simulation.|
|OPC||Optical Proximity Correction|
Reuse Methodology Manual. A set of guidelines that define good coding styles for HDL design.
Register Transfer Level, the point where the design is written as a register transfer description. A register transfer description is a type of a behavioral description which is closely related to the hardware implementation. The description is written in terms of register banks and combinational logic.
A software tool that performs a predefined set of fixed checks on a coding language such as Verilog, VHDL, C or C++.
Joint Test Access Group
A consortium of individuals from North American companies whose objective is to tackle the challenges of testing high density IC devices.
Hardware Description Language, a programming language like way of describing hardware. The two most common HDL's are Verilog and VHDL.
|The Accellera Formal Verification Technical Committee has been created to develop and promote a property specification language compatible with Verilog (IEEE-1364) and VHDL (IEEE-1076). Visit: www.accellera.org for further information.|
Bus functional models, a piece of software designed to mimic the behavior of a hardware interface device.
|PCD||Process Control Document|
|PCM||Process Control Module|
|SCM||Scribeline Control Module|
|LAMP||LAMP is an acronym for a solution stack of free, open source software, originally coined from the first letters of Linux (operating system), Apache HTTP Server, MySQL (database software) and Perl/PHP/Python, principal components to build a viable general purpose web server.|
|TLM||Transaction-level modeling (TLM) based design and verification in advanced IC technology.|
|OVM||The Open Verification Methodology (OVM) is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on two-thirds of the world's SystemVerilog simulators. The OVM will also facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e (IEEE 1647) languages. On 18 December 2009, OVM 2.1 was released to OVM World.|
|LEC||LEC is nothing but Logic
Equivalence checking. LEC can be done with Conformal, Formality, Formal
PRo tools. It is basically checking functionality between RTL and
You can check the functionality between pre-layout netlist and post layout netlist just to make sure that Place & Route tool didn't mess up anything.
|UPF||Unified Power Format, Quick reference, current version is 1.0|
|CPF||Common Power Format, Quick Reference, Example coding|
|IBIS||I/O Buffer Information Specification|
|SDC||Synopsys Design Constraints.|
|SDF||Standard Delay Format (SDF) 1.0, 2.0, 3.0, 4.0|
|SPEF|| Standard Parasitic
Exchange Format (SPEF) is an IEEE
standard for representing parasitic data of wires in a chip in ASCII
format. SPEF is most popular specification for parasitic
between different tools of EDA domain during any phase of design.
SPEF is an Open Verilog Initiatve (OVI)--and now IEEE--format for defining netlist parasitics. SPEF is NOT identical to the SPF format, although it is used in a similar manner. Like the SPF format, SPEF includes resistance and capacitance parasitics. Also like the SPF format, SPEF can represent parasitic in detailed or reduced (pi-model) forms, with the reduced form probably being more commonly used. SPEF also has a syntax that allows the modeling of capacitance between different nets, so it is used by the PrimeTime SI (crosstalk) analysis tool. SPEF is smaller than SPF and DSPF because the names are mapped to integers to reduce file size.
The Difference Between Parasitic Data Formats SPF, DSPF, RSPF, SPEF, and SBPF
Standard Parasitic Format
(DSPF) is a very different format,
meant to be useful in a SPICE simulation. For example, NET sections do
not have endings, and comments should start with two asterisks.
DSPF models a detailed network of RC parasitics for every net. DSPF is therefore more accurate than RSPF, but DPSF files can be an order of magnitude larger than RSPF files for the same design. In addition, there is no specification for coupling caps in DSPF. DSPF is more similar to a SPICE netlist than the other formats.
Format (SPF). SPF is a Cadence Design
Systems standard for defining netlist parasitics. DSPF and RSPF are the
two forms of SPF; the term SPF itself is sometimes used (or misused) to
represent parasitics in general. DSPF and RSPF both represent parasitic
information as an RC network.
Parasitic Format (RSPF). RSPF represents
each net as an RC "pi" model, which consists of an equivalent
”near" capacitance at the driver of the net, an equivalent
capacitance for the net, and an equivalent resistance connecting these
two capacitances. Each net has a single "pi" network for the network,
regardless of how many pins are on the net. In addition to the pi
network, RSPF causes the PrimeTime tool to calculate an Elmore delay
for every pin-to-pin interconnects delay.
|SBPF||SBPF is a Synopsys
binary format supported by PrimeTime.
Parasitic data converted to this format occupies less disk space and
can be read much faster than the same data stored in SPEF format. You
can convert parasitics to SBPF, by reading them in and then writing
them out with the write_parasitics -format sbpf command.
|DEF||Design Exchange Format (DEF) from Silicon Integration Initiative Inc. (Si2) and Cadence, customers will be able to download for free from the OpenEDA Web site. Both DEF and LEF belong to physical design formats.|
|LEF||Library Exchange Format (LEF) from Silicon Integration Initiative Inc. (Si2) and Cadence, customers will be able to download for free from the OpenEDA Web site.|
|SVRF||Standard Verification Rule Format (SVRF) This is the programming language for Mentor Graphics semiconductor physical verification tools, like Calibre|
||Results Viewing Environment (RVE) is the interface and environment for checking the calibre output for drc and lvs results .|
|Market Landscape/ Product Definition||How to undedrstand existing market landscape and to execute an excellent product definition/design||PDK101 Internal|
|Design Resources||All IC design related resource||OPEN to public for feedback and review.|
|Silicon Technology and Foundry Fab Zone||Silicon technologies for now, will add III-V technology later on.||OPEN temporary to public for feedback and review.|
|EDA Zone||EDA/CAD/PDK information||OPEN to public for feedback and review|
|Device and Component||All kind of high performance devices and component from technologies and companies.||NOT yet online for now.|
|SPICE/MODEL||SPICE model for all kind of devices||OPEN to public but under construction|
|IPfarm© Area||All sort of soft and hard IP blocks for circuit design and IP developer information and entry page.||OPEN to public but constantly construction|
|ESD, Reliability, and Failure||ESD, reliability and failure knowledge and case study||OPEN to public for feedback and review|
|Product Test/Manufacture||Product manufacturing, packaging, and testing information||NOT online for now|
|Project Management||All essential ideas and best practice for project management||PDK101 Internal|
|Marketing and Sale||Marketing and sale related materials||PDK101 Internal|
|Cad syntax example syntax exampleence Assura||Official Cadence Web page|
|Mixed Signal SOC design flow||Mentor Mixed signal
design flow doc
|Cadence Tools Docs||Online Cadence tool pdf files.|
|Synopsys Nanosim doc||Online Synopsys Nanosim pdf files.|
|Demo on Demand||Online demo from service providers|
|DeepChip EDA group||Online ESD discussion group. Lot of useful info.|
|OPENCORES||Open source IP repository|
|Design/IP Reuse||Online Design reuse and IP service provider|
|Agilent Online Demo||Online Agilent EDA demo|
|Xilinx design reuse document||Xilinx design resue Document.|
|TechOnLine||many useful educational tools for EE and IT|
|A organization focuses on improving productivity and reducing cost in creating and producing integrated silicon systems.|
||OpenEDA.Si2.org is a restricted access site for the distribution of licensed materials from Si2 development groups (councils, projects, boards, or workgroups).|
|OpenAccess||OpenAccess is a community effort to provide true interoperability, not just data exchange, among IC design tools through an open standard data API and reference database supporting that API for IC design.|
|SoC Central||SOCcentral brings you the latest new about SOC/ASIC/FPGA design, EDA tools, design methodologies, intellectual property (IP), and design reuse.|
|eg3||Online discssion group|
|EDAboard||Online Analog IC design and layout discussion forum.|
|EEtimes||Online EEtimes website
|Design-reuse||Design resue website.|
|IC Design Quality Checklist||IC design quality on design magazine.|
|EDA Geek||EDA Geek publishes news about the electronic design automation and semiconductor industry.|
|Cadence_Community Forum||Cadence Community Forum for Cadence tool users.|
|AlteraForum||A lot of good FPGA and EDA general information and discussion|
|Low Power Design||Low power design|
|eecatalog||some useful and informative video clips about IC design and silicon technology.|
|low-powerwireless.com||Low power design specific on wireless system.|
|CADFORUMS.COM||All AutoCad and Cad related discussion|
|Softpedia||An lot of GPL EDA software codes and script for generic purpos|