All Electronic Design Automation (EDA) products and information      
                                                                                            First created Oct. 11 2009

                                                                                            Last Update March 12 2014
                                                                                            by Martin Chu,

Major EDA/CAD tools flow providers:
Mentor Graphis
MAGMA Design Automation                                                                                            

Commonly used EDA Tools for full customer IC design

(Member only)

Design Database Management and IP quality  validation/management (Member only)

Script and Programming Languages for Design Automation and Productivity Enhancement

EDA’s Dr. Jekyll and Mr. Hyde  Very good overall prospective view about EDA tools and their interface exchange format. EDA and CAD junior engineers should review this web posting as soon as possible. 

Cadence connection/interface solution providers

Important information:and fundamental issues need to address for Design House (supposed for Member only, temporaryly open to public for information sharing, reviewing and feedback)
I categirized  Design/CAD projects into five categories:  Design, PDK,  IP, Methodology, Tools. I will update this section as new findings or needs shown up.

Design Project data structure
Design Database version control, archieve and retrive methodology
Circuit simulation automation and scripting: ( Digital and Mixed Signal flow)
Design specification, Deliverables Review flow, action tracking, content audit, sign-off procedure and methodology.
Convert or migrate a designs in old Cadence database (CDBA)  to  new  Cadence OPEN ACCESS database (somewhat important)
Convert or migrate a designs between Cadence and non-Cadence database  (less important)

PDK data structure,  mature status, tagging, version control, update and release methodology
GSA_mixed_signal and RF SPICE MODEL checklist
PDK elements and package Quality Control flow
CAD basic QA cell creation.
PDK QA cell  list
Digital Library Characterization

System and EDA/CAD Software Tool version, configuration and update control
Commonly used EDA/CAD software evaluation and new version validation.
(Perl, tcl, SKILL, python, ruby, SWIG  etc basic info)
System software, EDA software, and Cadence version compatability matrix
Database management software including Cadence design database.

IP (including digital library)
IP specification, validation and qualification procedure
IP quality status, tagging and Design/IP Database Management
IP release and control mechanism   
IP creation, documenetation and Design Project Management
Digital library characterization,

Evaluation and Implementation of Cadence design database data management (DDM) and current solution available on the market.
Analog and Mixed Signal Design flow, requirement and concerns
Digital Design Flow, requirement and concerns
RF Design Flow, requirement and concerns
Final mask pattern generation and Boolean operation validation.
RTL to GDS flow or (physical implementation) with Analog and Mixed Signal design block in mind (new added on Jan 2011)
Currently available RTL to GDS tools, flow and solutions provided three major EDA communities.
Standardize of  software coding,  RTL and test bench naming convention and best practice.


Pretty Good EDA Design Flow from industrial Foundry (TSMC as of 2011)
You may think this as the industrial standard and suggested design flow.
TSMC Open Innovation Platform  -> This has very good EDA/PDK/IP related information

TSMC Digital Reference Flow 11.0  (released at SAN JOSE, Calif. – June 9, 2010)

These are what  TSMC Digital Reference Flow 11.0 covered.
  • Timing Closure Flow
  • Hierarchical Flow
  • Signal Integrity Closure Flow
  • Power Closure Flow
  • Advanced Low Power Management
  • Enhanced DFM
  • Enhanced SSTA
  • DFM Auto Fixing Flow
  • Transparent Half Node
  • System-in-Package (SIP)
  • Electronic system level (ESL) design

Reference Flow 11.0 includes Apache’s recently announced ESD integrity solution, PathFinder. In addition, Apache’s products for power and noise analysis were validated for Reference Flow 11.0 in the areas of System-in-Package (SiP), 3D-IC with Through Silicon Via (TSV), and RTL power estimation:

  • PathFinder™ for full-chip ESD verification supporting human body model (HBM), machine model (MM), and charged device model (CDM)
  • Chip Power Model (CPM™) and Chip Thermal Model (CTM) for compact die modeling used in SiP and 3D-IC/TSV analysis
  • RedHawk’s native support for concurrent analysis of multiple dies with different process technologies
  • PowerArtist for RTL to gate –level power estimation and correlation
TSMC Analog/Mixed Signal (AMS)  Flow 1.0 (released at SAN JOSE, Calif. – June 9, 2010)
AMS Reference Flow 1.0 includes Apache’s Totem platform, a power, noise, and reliability solution for analog, mixed-signal, memory, and high-speed I/O designs. In the Reference Flow, Totem is selected for early power/ground (P/G) grid integrity check, static and dynamic IR drop signoff, electro-migration (EM) validation, and chip power model (CPM™) generation of full custom designs.


Some interesting software for EDA purpose

SWIG is an interface compiler that connects programs written in C and C++ with scripting languages such as Perl, Python, Ruby, and Tcl. It works by taking the declarations found in C/C++ header files and using them to generate the wrapper code that scripting languages need to access the underlying C/C++ code. In addition, SWIG provides a variety of customization features that let you tailor the wrapping process to suit your application.

SWIG  quick tutorial

Useful Verification method usd in EDA flow
Assertion-Based Verification

Basic concerns and guidelines for any system or tool integration effort.:

Any recommendations or suggestion, please email to
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