Commonly used EDA Tool for full custom IC design sorted by Company names
created and maintained by Martin Chu 
Last Updated on Oct 6 2012 


First Encounter Virtuall prototyping and Design Planning
SoC Encounter place and route, suitable for analog and mixed signal SOC Chip final placement and routing.  
Fire & Ice QXC RC parasitic extraction commonly used in Cadence SoC encounter flow. (somewhat old tool) as of 2008
VoltageStorm power analysis, Voltage and IR drop, Can do some noise coupling for analog and mixed signal design. 
Conformal-LC Formal verification
Nanaometer Delay  calculator  (NDC)
SI noise,  glitch and Crosstalk analysis. Old tool as view from Year 2009.
A lot of EDA expert call this tool  the "perfect" signal-integrity tool (in EEtimes 2004). .
Assura and old Dracula LVS/DRC physical verification and PEX extraction. Current , useful yet expensive physical verification tool. Somewhat difficult and heavy to support and maintain! Need expert and experienced engineer to support!
QRC   LVS/DRC physical verification and PEX extraction. Enhanced version of Assura. Cadence claims to be the industry’s premier 3D full-chip parasitic extractor.
Silicon Ensemble Place and route tool.  Typically  for standard Cell designs and small block design block place and routing!
Verilog-XL  Cadence Verilog simulator 
 Aptiva Corner and/or parameter simulation pass-fail specification environmental setup and simulation  flow.
 Spectre Accurate SPICE circuit simulator
 Affirma Cadence Analog/Mixed signal simulation flow
 Virtuso Custom Layout Design tool
 UltraSim  Fast Circuit simulator 
 AMS Designer Analog and Mixed signal /Digital co-simulation design system.
 RTL Compiler RTL Syntesis
 Encounter  (Nanoroute) Place, CTS and Route
Allegro  PCB Design Software

Design Compiler Logic/RTL  synthesis
Physical Compiler physical synthesis
Jupiter, or Jupiter XT floorplanner, Prototyping and Design Planning
Astro, IC Compiler automatic place and route
AstroRail and Astro XTalk signal integrity or cross talk analysis
STAR-RCXT RC parasitic extraction tool
Formality Formal verification tool
PrimeTime Static Timing analysis. PrimeTime is almost the industrial standard tool for sig-off sign-off.
Hercules LVS/DRC physical verification tool
NanoSim Fast SPICE simuator
TimeMill  Timeing simulator
PowerMill  Power simulator
HSPICE Circuit simulator
Raphael NXT 3D fast field solver extraction 
CC CMP Design for  Manufacture (DFM)
Cosmos Library Development and Full Custom Design
DFT Compiler, Tetra MAX  DFT and ATPG
PrimeTime-SI EM and  signal integrity analysis
PrimeTime PX, PrimeRail Power & IR Drop Analysis

Mentor Graphics
Calibre LVS/DRC physical verification
RC parasitic extraction
ADVanceMS Mixed signal simulation flow to support VHDL, VHDL-AMS, Verilog and SPICE
ModelSim Digital RTL code simulator
Advanced Simulation Environment
Eldo analog SPICE simulator
Olympus-SoC Place and Route tool
Fast-SPICE simulator

Magma Design Automation Inc. 
(on Feb 22 2012  acquired by Synposis)

Talus Design RTL Synthesis.  Talus® Design is an RTL-to-placed-gates design environment that provides RTL synthesis, DFT rule checking, concurrent timing analysis, and physical synthesis.  Available in 32/28-nm node
Talus RTL Talus RTL is a comprehensive RTL synthesis solution that can be used standalone or integrated within Magma’s Talus IC implementation system. It is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process without sacrificing design quality or the delivery schedule. When used in conjunction with the Talus Vortex physical implementation tool it dramatically improves the productivity of chip architects and logic designers while shortening turnaround time.
Talus Vortex Place, CTS and Route.  Talus® Vortex is a complete netlist-to-GDSII chip implementation system providing optimization, place and route capabilities, useful skew clock generation, floorplanning, power planning, RC extraction, and built-in incremental timing analysis.
Talus Design (DFT)  Magma DA's DFT and ATPG implementation. 
Talus Flow Manager  The Talus® Flow Manager (TFM) is a reference flow generator that provides Magma users with up-to-date, relevant, and best practice uses of the core technologies of Magma in an easy manner.
Talus Power Pro Talus® Power Pro, a key component of Magma’s integrated IC implementation platform, provides a comprehensive RTL-to-GDSII solution for power optimization and management.Talus Power Pro enables optimal power management throughout the flow with power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution. Talus Power Pro is fully integrated with Magma’s implementation flow to provide continuous power, timing and area tradeoffs throughout the design flow.
Talus Power Pro Talus® Power Pro, a key component of Magma’s integrated IC implementation platform, provides a comprehensive RTL-to-GDSII solution for power optimization and management.Talus Power Pro enables optimal power management throughout the flow with power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution. Talus Power Pro is fully integrated with Magma’s implementation flow to provide continuous power, timing and area tradeoffs throughout the design flow.
Tekton Tekton is a next-generation STA tool. It provides groundbreaking multi-mode/multi-corner performance on single CPU machines, delivering timing updates for tens of millions of instances in minutes. It provides full support for crosstalk analysis and AOCV and offers an embedded SPICE engine when extremely high accuracy is required.
Titan ADX, Titan LAX, Titan AVP, Titan SBR, Titan Mixed-Signal
These are all Magma Design Automation analog and mixed EDA tool.
Magma Blast Fusion Blast Fusion is used for the hierarchical design of large integrated circuits (ICs) and systems-on-chip (SoCs). This is a very good, and production-proven RTL-to-GDSII flow.
The Magma Blast Fusion consists of Tcl interpreter, a sophisticated graphical user interface (GUI), and several  design engines.
Hydra Prototyping & Design Planning
Quartz Time Static Timing Analysis
Qauls Power Pro, and Quartz Rail
Power & IR Drop Analysis     
QuickCap  or
QuickCap NX
QuickCap® is the gold-standard 3D capacitance extractor for integrated circuits. It is used by most of the world’s major silicon manufacturers for accurate parasitic extraction.  
QuickCap® NX is the next-generation 3D parasitic extractor for critical circuit analysis. QuickCap NX is built on QuickCap, the gold standard for extraction, and includes key capabilities that allow the tool to address design challenges that occur in 90-nm and smaller process technologies.  In short, both are parasitic capacitance extraction and validation tools.
Quartz DRC/LVS DRC/LVS or  physical verification tools.
Quartz RC RC parasitic extraction.
FineSim FineSim™ SPICE is a SPICE-level simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed signal and analog designs.
SiliconSmart SiliconSmart® is Magma's standard cell and IO characterization solution used to generate timing, power, ccs, ecsm, SI (noise) and low power libraries.
Camelot is a CAD navigation, or database interafce and exchange system and database management tool. It also has fab analysis capability.

EEsof EDA Agilent EEsof EDA is the leading supplier of Electronic Design Automation (EDA) software for communications design. High-frequency, high-speed, device modeling, signal-processing and RF circuit design engineers create better products faster using design flows built on our system, component, and physics-level design tools.
Advanced Design System (ADS)
Advanced Design System is the leading electronic design automation software for RF, microwave, and high speed digital applications. ADS pioneers the most innovative and commercially successful technologies, such as X-parameters* and 3D EM simulators, used by leading companies in the wireless communication & networking and aerospace & defense industries. For WiMAX™, LTE, multi-gigabit per second data links, radar, & satellite applications, ADS provides full, standards-based design and verification with Wireless Libraries and circuit-system-EM co-simulation in an integrated platform.
IC-CAP Integrated Circuit Characterization and Analysis Program (IC-CAP) is the industry standard for DC and RF semiconductor device modeling. IC-CAP extracts accurate compact models used in high speed/digital, analog and power RF applications. Today’s most advanced semiconductor foundries and IDMs rely on IC-CAP for modeling silicon CMOS, Bipolar, compound gallium arsenide (GaAs), gallium nitride (GaN) and many other device technologies. IC-CAP is the most advanced, customizable modeling software and includes measurement, simulation, optimization and statistical analysis tools. 
Momentum Agilent's Momentum is the leading 3D planar electromagnetic (EM) simulator used for passive circuit modeling and analysis. It accepts arbitrary design geometries (including multi-layer structures) and uses frequency-domain Method of Moments (MoM) technology to accurately simulate complex EM effects including coupling and parasitics. Accurate EM simulation enables RF/MMIC designers, RF/High-Speed Board Designers, RF Module/SiP Designers and Antenna Designers to improve design performance and increase confidence that the manufactured product will meet spec. Momentum is also integrated with ADS and Genesys, along with third party tools from Cadence, Mentor and Zuken.
Electromagnetic Professional (EMPro) is Agilent EEsof EDA's EM simulation software design platform for analyzing the 3D electromagnetic (EM) effects of components such as high-speed and RF IC packages, bondwires, antennas, on-chip and off-chip embedded passives and PCB interconnects. EMPro EM simulation software features a modern design, simulation and analysis environment, high capacity simulation technologies and integration with the industry’s leading RF and microwave circuit design environment, Advanced Design System (ADS) for fast and efficient RF and microwave circuit design.
Genesys Easy-to-use and easy-to-learn, Genesys is the low-cost, high-performance integrated electronic design automation software for RF/microwave circuit board and subsystem designers. As a proven safe investment with an installed base of 5,000 satisfied designers, Genesys literally pays for itself through cost savings within its first year of deployment. As the designer’s needs grow beyond RF board applications, Agilent provides full trade-in credit toward the purchase of Advanced Design System for designing MMIC and multi-technology RF system-in-package modules.
SystemVue is a focused electronic design automation (EDA) environment for electronic system-level (ESL) design. It enables system architects and algorithm developers to innovate the physical layer (PHY) of wireless and aerospace/defense communications systems and provides unique value to RF, DSP, and FPGA/ASIC implementers. As a dedicated platform for ESL design and signal processing realization, SystemVue replaces general-purpose digital, analog, and math environments. SystemVue "speaks RF", cuts PHY development and verification time in half, and connects to your mainstream EDA flow.
GodenGate GoldenGate RFIC Simulation and Analysis Software is the most trusted simulation, verification and analysis solution available for integrated RF circuit design. Its unique simulation algorithms enable full characterization of complete transceivers prior to tape-out. Frequency- and time-domain techniques are used to accurately verify the most complex RFIC - Wireless design performance. To ensure device manufacturability and reduce design spins, GoldenGate automates the simulation, control and analysis of complex verification schemes. GoldenGate RFIC Simulation and Analysis Software is fully integrated into the Cadence Analog Design Environment.

Apache Design Automation

PowerArtist PowerArtist™ is an RTL design-for-power platform providing fully-integrated, advanced power analysis and automatic power reduction technologies.
RedHawk™ RedHawk™ is a full-chip, dynamic power analysis and sign-off solution for high-performance SoCs, including advanced low-power design.
Totem Totem™ is a fully-integrated, layout-based power and noise platform for analog, mixed-signal, memory, and high-speed I/O designs.
Sentinel™ Sentinel™ is a complete chip-package-system co-design/co-analysis solution addressing the system-level power integrity, I/O-SSO, thermal, and EMI challenges.
PathFinder™ PathFinder is the industry’s first comprehensive layout-based electro-static discharge (ESD) integrity solution targeted to address the increasing reliability challenges faced by nanometer designs. PathFinder integrated modeling, extraction, and simulation capabilities enables automated and exhaustive analysis of the entire IC, highlighting weaknesses in the design that can be susceptible to failure caused by an ESD event. It also provides innovative transistor-level dynamic ESD capabilities for validation of I/O, analog, and mixed-signal designs.
Delivering full-chip capacity and SPICE-like accuracy, PathFinder enables designers to perform early prototyping, circuit optimization, and full-chip signoff. It helps designers identify the most vulnerable area of the design, meet ESD guidelines, and improve product yield.

Free Simulators

  • Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well. All my tutorials are compiled on this compiler.
  • Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.
  • Cver : Cver is an interpreted Verilog simulator. It follows the 1995 IEEE P1364 standard LRM with some features from Verilog 2000 P1364 standard. Although, because it is used in large company design flows, various changes from the P1364 standard have been made to match results of other simulators. It implements full PLI including PLI vpi_ application programing interface (API) as defined by Verilog 2000 LRM.
  • Verilogger : The evaluation version is a free 1000 line free Verilog simulator plus an automatic test bench generation tool. Student versions start at $70 for 6 months.
  • Veriwell : This is a very good simulator. Supports PLI and verilog 1995.

VCD Viewer

  • Waview : Free multi platform VCD waveform viewer.
  • nWave : One of the best VCD viewer, with support for large VCD dumps.
  • Undertow : Undertow waveform viewer.
  • GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
  • Dinotrace : Freeware VCD viewer from veritools
  • WaveViewer : SynaptiCAD's freeware VCD viewer also supports analog signal display and SPICE import. A proprietary compressed waveform format allows it to compress VCD files by 200x, making it a very fast viewer.

Code Coverage

  • Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process. These tools include HDL checking, coverage analysis, test suite analysis and FSM analysis. The environment includes an extensible flow manager for easy incorporation of custom verification flows. Verification Navigator supports Verilog, VHDL and mixed language designs and integrates seamlessly with all leading simulation environments.
  • SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design. Verisity's SureCov measures FSM and code coverage with the lowest simulation overhead of any tool available, and without requiring changes to the source design. The SureSight graphical user interface shows exactly which parts of the design have been covered and which have not.
  • Code Coverage Tool : A freeware code coverage tool. Code coverage tool is a Verilog code coverage analysis tool that can be useful for determining how well a test suite is covering the design under test.


  • Leda : Leda is a code purification tool for designers using the Verilog® and VHDL Hardware Description Language (HDL). Leda is uniquely qualified to analyze HDL code pre-synthesis and pre-simulation and is totally compatible with all popular synthesis and simulation tools and flows. By automating more than 500 design checks for language syntax, semantics and questionable synthesis/simulation constructs, Leda detects common as well as subtle and hard-to-find code defects, thus freeing designers to focus on the art of design.
  • HDLint : A power full linting tool for VHDL and Verilog.
  • nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system.
  • SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks the most complete lint tool on the market.


  • Teal : open source c++ class library for verification
  • Jove : The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language. Jove has been tested extensively with Synopsys VCS and to a lesser extent with the GPL version of cver by Pragmatic C Software.
  • FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs.
  • TestBencher Pro : Generates bus-functional models and test benches from language independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. Generates code for Verilog, VHDL, and SystemC.
  • Timing Diagrammer Pro : A professional timing diagram editor with an unbeatable feature set. Performs true full-range min/max timing analysis to help you find and eliminate all timing violations and race conditions. Also automatically calculates critical paths and adjusts for reconvergent fanout. Inserting diagrams into word processors is painless, thanks to a variety of image capture formats.
  • TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams. The waveforms can easily be exported to other Window programs, such as Microsoft Word, for use in writing design specifications. TimeGen is less price compared to other tools.
  • WaveFormer Pro : Generates VHDL, Verilog, and SPICE code, and Patter Generator stimulus from timing diagrams. Import waveforms from HDL simulators, HP logic analyzers, VCD files, or draw them using the built-in timing diagram editor. Automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing, perform RTL level simulation, and generate synthesizable models directly from Boolean and registered logic equations.
  • Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation.
  • Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.
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