Free Simulators

• Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well. All my tutorials are compiled on this compiler.
• Verilator : Verilator is a compiled cycle-based simulator, which is free, but performs as fast as the commercial products.
• Cver : Cver is an interpreted Verilog simulator. It follows the 1995 IEEE P1364 standard LRM with some features from Verilog 2000 P1364 standard. Although, because it is used in large company design flows, various changes from the P1364 standard have been made to match results of other simulators. It implements full PLI including PLI vpi_ application programing interface (API) as defined by Verilog 2000 LRM.
• Verilogger : The evaluation version is a free 1000 line free Verilog simulator plus an automatic test bench generation tool. Student versions start at $70 for 6 months.
• Veriwell : This is a very good simulator. Supports PLI and verilog 1995.

VCD Viewer

• Waview : Free multi platform VCD waveform viewer.
• nWave : One of the best VCD viewer, with support for large VCD dumps.
• Undertow : Undertow waveform viewer.
• GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers.
• Dinotrace : Freeware VCD viewer from veritools
• WaveViewer : SynaptiCAD's freeware VCD viewer also supports analog signal display and SPICE import. A proprietary compressed waveform format allows it to compress VCD files by 200x, making it a very fast viewer.

Code Coverage

• Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process. These tools include HDL checking, coverage analysis, test suite analysis and FSM analysis. The environment includes an extensible flow manager for easy incorporation of custom verification flows. Verification Navigator supports Verilog, VHDL and mixed language designs and integrates seamlessly with all leading simulation environments.
• SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design. Verisity's SureCov measures FSM and code coverage with the lowest simulation overhead of any tool available, and without requiring changes to the source design. The SureSight graphical user interface shows exactly which parts of the design have been covered and which have not.
• Code Coverage Tool : A freeware code coverage tool. Code coverage tool is a Verilog code coverage analysis tool that can be useful for determining how well a test suite is covering the design under test.

Linting

• Leda : Leda is a code purification tool for designers using the Verilog® and VHDL Hardware Description Language (HDL). Leda is uniquely qualified to analyze HDL code pre-synthesis and pre-simulation and is totally compatible with all popular synthesis and simulation tools and flows. By automating more than 500 design checks for language syntax, semantics and questionable synthesis/simulation constructs, Leda detects common as well as subtle and hard-to-find code defects, thus freeing designers to focus on the art of design.
• HDLint : A power full linting tool for VHDL and Verilog.
• nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system.
• SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks the most complete lint tool on the market.

Utils

• Teal : open source c++ class library for verification
• Jove : The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language. Jove has been tested extensively with Synopsys VCS and to a lesser extent with the GPL version of cver by Pragmatic C Software.
• FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs.
• TestBencher Pro : Generates bus-functional models and test benches from language independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. Generates code for Verilog, VHDL, and SystemC.
• Timing Diagrammer Pro : A professional timing diagram editor with an unbeatable feature set. Performs true full-range min/max timing analysis to help you find and eliminate all timing violations and race conditions. Also automatically calculates critical paths and adjusts for reconvergent fanout. Inserting diagrams into word processors is painless, thanks to a variety of image capture formats.
• TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams. The waveforms can easily be exported to other Window programs, such as Microsoft Word, for use in writing design specifications. TimeGen is less price compared to other tools.
• WaveFormer Pro : Generates VHDL, Verilog, and SPICE code, and Patter Generator stimulus from timing diagrams. Import waveforms from HDL simulators, HP logic analyzers, VCD files, or draw them using the built-in timing diagram editor. Automatically determine critical paths, verify timing margins, adjust for reconvergent fanout effects, and perform "what if" analysis to determine optimum clock speed. WaveFormer Pro also lets you specify and analyze system timing, perform RTL level simulation, and generate synthesizable models directly from Boolean and registered logic equations.
• Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation.
• Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.