RTL to GDSII flow (or also called physical implementation) currently supported by three major EDA company

Created by Martin Chu
First created 20140304
Last update Not yet

Cadence solution:
SoC Encounter RTL-to-GDSII System (specification from Cadence)   

Full-chip implementation in a single system
The SoC Encounter System provides fast and flexible feasibility analysis, giving engineers an early, accurate view of whether the most complex designs will meet their targets and be physically realizable. It offers the latest low-power design and yield capabilities and provides a predictable path to design closure.

With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs.
Features Benefits
  • Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis
  • Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design
  • Provides a statistical static timing analysis solution and standardized ECSM library models
  • Incorporates cutting-edge yield and low-power design capabilities
  • Handles 50M+ gate designs at 90nm and below
Cadence SOC Encounter flows as "a complete front to back solution," including RTL and gate-level simulation and equivalence checking. The flow includes power optimization through clock-gating insertion, as well as proven prevention of signal-integrity problems through analysis and repair.

The reference flow incorporates the following Cadence tools:

The Cadence SoC Encounter System
Encounter RTL Compiler global synthesis
CeltIC NDC  
Cadence NanoRoute router
VoltageStorm power grid verification
Encounter Conformal verification technologies
Cadence QRC Extraction
Assura DRC/LVS physical verification.

ARM and Cadence Reference Flow detail description
:
REFERENCE METHODOLOGY PROCESS-OVERVIEW
The ARM-Cadence Encounter Reference Methodology is a set of Tcl scripts that enable users to implement  soft core IP quickly, without detailed knowledge of the tool options used by the flow. The underlying directory structure provides a concise and intuitive way of managing the ARM processor hardening flow. For expert users, detailed documentation describes the steps they can use to adjust the flow. .



Synposys Solution:
Synopsys Announces Advanced Techniques in TSMC Reference Flow 8.0 That Address 45nm Design Challenges June 4, 2007  source: http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&&newsid=2203&&newsdate=2007/06/05&&language=E
 
TSMC Reference Flow 8.0 includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies. Advanced power management techniques include multi-voltage and MTCMOS power gating, as well as more commonly used techniques available through the Synopsys Galaxy Design Platform such as clock gating and multi-threshold. Reference Flow 8.0 performs comprehensive dynamic and leakage power optimization and analysis throughout the synthesis, physical design and sign-off phases of the design process.
"Our design platforms supporting TSMC Reference Flow 8.0 enable designers to address complex, deep-submicron challenges," said Rich Goldman, vice president of strategic market development at Synopsys. "Our continued relationship with TSMC provides our mutual customers with a comprehensive, low-risk solution from RTL to silicon."

The Synopsys Discovery Verification platform enables power-aware simulation, formal equivalence checking, and static analysis of designs that use advanced power management techniques such as multiple power domains, level shifters, isolation cells, and retention memory elements. More than 10 advanced multi-voltage designs have been taped out with TSMC's manufacturing technology using Synopsys power management solutions. The complete low-power flow is compatible with current Synopsys commands and the emerging Unified Power Format (UPF) standard for low-power intent.

"Through the years, Synopsys and TSMC have worked together to meet the evolving challenges of deep submicron design," said Kuo Wu, deputy director of design service marketing at TSMC. "Manufacturability, yield, and leakage are vital design concerns at the 45-nanometer node. The combination of TSMC Reference Flow 8.0 and Synopsys' tools and platforms address these concerns."

Reference Flow 8.0 also takes advantage of new capabilities available through the Galaxy Design Platform and PrimeYield design-yield analysis tool suite for 45nm readiness. For productivity gains during implementation, PrimeYield LCC enables designers to use concurrent yield optimization for critical area reduction and automated hot-spot fixing within IC Compiler. For analysis, designers can now perform parametric (timing) analysis in addition to functional hot-spot analysis. To enable this, the PrimeYield and Star-RCXT™ tools support advanced features such as TSMC's VCMP (virtual CMP) analysis engine.

Synopsys has worked together with TSMC on a comprehensive variation-aware design flow that allows designers to reduce margins, improve design robustness, and enhance parametric yield. The Synopsys variation-aware analysis solution consists of three important components: The Composite Current Source (CCS)-based statistical library, sensitivity-based extraction using the Star-RCXT VX tool and statistical timing analysis technology in the PrimeTime® VX tool. With uncertainties introduced by the wide variation in device and interconnect at the sub-45nm level, customers can apply this solution to their complex 45nm System-on-Chip (SoC) designs today. Additional Synopsys enhancements featured in TSMC Reference Flow 8.0 include advanced design-for-test (DFT) capabilities and support of TSMC 45nm design rules.
About TSMC Reference Flow 8.0 Support
Reference Flow 8.0 incorporates comprehensive Synopsys-based RTL-to-GDSII using the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery™ Verification Platform with VCS®, HSPICE®, and HSIM™/Nanosim® for RTL verification and circuit simulation.

As an integral part of the reference flow, Galaxy support includes:
§ Design Compiler® and Design Compiler topographical technology logic synthesis
§ Power Compiler™ multi-voltage power management
§ Leda RTL Checker
§ DFT MAX 1-pass test synthesis
§ JupiterXT™ physical planning
§ IC Compiler physical implementation
§ PrimeTime, PrimeTime SI, and PrimeTime VX static timing and signal integrity sign-off
§ PrimeRail power network sign-off
§ PrimeTime PX full-chip power analysis
§ Star-RCXT extraction
§ Hercules™ PVS physical verification
§ TetraMAX® automatic test pattern generation (ATPG)
§ PrimeYield LCC for design-for-yield analysis

Galaxy SoC Implementation

Including PrimeTime, ICCompiler, Design Compiler, TetraMAX, Laker Layout, and HSPICE,

Synposis is  using  IC Validator/ StarRC to validate DRC and  RC extraction. 

Interfaces

  • Library Interface
    • Reads LIB synthesis library containing functionality, timing, and design rule constraints
    • Reads Milkyway (MWY) physical library describing technology and cell outlines
    • Reads LEF, technology file (TF) format
  • Inputs
    • Verilog netlist
    • SDC, DEF, SPEF, SBPF
    • Several user-level commands are provided for specifying and modifying the floorplan
  • Outputs
    • Verilog netlist
    • SDC, DEF, SPEF, SBPF
    • GDSII
    • OASIS
  • User Interfaces
    • Tcl or GUI-based user interface
    • All Design Compiler reports enhanced with physical information; additional reports and commands enable analyzing layout and checking consistency of libraries and input files 

Mentor Graphics Solution:

Olympus-SoC™  was originally developed to address the variability problems seen in digital IC design starting at 65nm. It claims The flexible architecture allows the software to fully support MCMM, low power, capacity and runtime, and manufacturing closure for the 32/28 nm node.

Olympus-SoC and Calibre InRoute are supported by all major foundries, including TSMC reference flow 11 for 28nm,[8] X-FAB Silicon Foundries for 35nm, STMicroelectronics, SMIC, UMC, and GLOBALFOUNDRIES.

Olympus-SoC supports the Unified Power Format (UPF)  throughout the netlist-to-GDSII flow, including the ability  to describe design intent through power state definition tables.


Magma® Design Automation Solution (Now is part of Synposys) 

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Some very successful RTL to GDS or ASIC Design flow
Faraday ASIC Design Methodology and Tools

What are the concern for RTL to GDS in general: 
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