How and what to control the quality of a PDK in a fabless design house
                                                                                       by Martin Chu,
                                                                                        First Created March 28 2010
                                                                                        Last Update May 16 2010

Fabless design houses depend on process PDK to design circuit and products.
The quality of PDK directly impact on the quality of the design and final products.
However, based on company resource, budget, time to market, the quality of PDK inside a fabless design house can be used and fall into the following three different stage.
Therefore,  the development of PDK and its QA flow also can be divided into these three levels.

I. The best and proactive PDK QA flow: for a mature and established technology 
(somewhat based on importance and priority)

* The accuracy of all SPICE models for supported and used devices are netlisted and SPICE tool/flow simulated and  verified.  The simulated result are verified against the ACTUAL/OFFICIAL silicon data. Any discrepancies  need to be expalined and documented.  
* All SPICE models for the design project should be up to date and aligned to silicon data. Prefer to have automatic script to run and verify and report QA result. SPICE simulation result using that model should match silicon data..

* There should be the following test benches for accurate SPICE simulation
        (a) Timing simulation usimg odd number of inverter to verify oscillating frequency. The best digital QA block is odd number of inverter array or ring oscillator. The frequemcy of oscillator can be used to determine cox and Ids accuracy.
        (b) An CMOS operation amplifier with known AC gain using know RC value to check AC simulation result.
        (c) Transfer function of  standard inverter with right W/L  P to N ratio.
        (d) Fourier transformation for a amplifier output 
        (e) Monte Carlo simulation test bench and script to validate all MOS, CAP, RES and Bipolar.
        (f) Process Corner simulation test bench and script for TT, FF, SS, FS, SF cases  for different temperature.
        (g) Noise and distortion simulation of a amplifier output
        (h) Power dissipation circuit vs clock frequency.
        (i) A large area and a perimeter NW/PW tank diodes to verify reverse leakage at different temperature.

* All digital library, IP and metal process option are aligned to the foundry current supported PDK elements. 
* All used and supported devices in the technology are DRC, LVS and ERC and antenna check clean.
* Foundry Mask making alothrim are aligned with the technology and process option specification for that project or PDK.
* Use industrial Standard EDA/CAD tools and Flow as much as possible.
* There should be a flow and methodology for regular design and that design flow is compatable with in-house IP creation flow.
* There should be a design reuse practice and design specification, testbench and simulation automation flow.
* System design knowledge should be also captured in the design flow.
* Best Practice knowledge buildup in a wikipage or Track webpage.
* Design/PDK/CAD Training tutorial and general infoamtion should be abalible within internal websites and constantly updated.    
* standardize for digital, analog and Mixed Signal design flow
* Design/PDK and layout database should be version controlled.
* VXL support  needs connectivity in supported devices
* Design flow and EDA system should take care of tool version and PDK version.
* Design migration and Cadence version migration (Cadence 442, CDS446, CDS5.1 and OpenAccess)
* specman and design specification in XML, test bench for design verification.
* Design parameters setup, value and TB and environment configuration.
* Common and intuitive GUI        
                Use DA and methodology  for project setup and design quality control
* Artisan project setup 
* There should be one digital synthesis test script  for timing analysis validation. This depends on whether  the technology is more toward digital design in nature or not.
* Access ability and control


II.  The fastest, patch and reactive for an acceptable PDK QA flow. The same as above requiremets except the following
* Design/layout version control function.
* automatic script to run PDK QA and result report.
* Artisan project setup
* Design flow compatable with IP creation.
*  Access ability and control
* In order for smooth adoption and implementation of new system, there should be stages for CAD/PDK development Project within company
      - Short
      - Medium
      - Long


PDK QA presentation for a silicon wafer Foundry company.


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