How to design a sigma-delta ADC
source: http://www.edaboard.com/ftopic99811.html   
--------------------------------------------------------------------------------
 
There are two useful books for delta-sigma modulation:

Oversampling Delta-Simga Data converters (edited by Candy and Temes) also called " the blue book"
Delta-Sigma Data Converters (edited by Norsworthy el), also called "the yellow book".

Try to locate these two books. Blue book is collection of journal and conference papers from IEEE, if you have access to IEEE explore, you can download them as well.

My experience tells the right way to master delta-sigma modulation is:

1. first you need to feel very comfortable with control theory, digital signal processing. They are the fundamentals. Delta-simga is only of their applications.

2. Learn matlab first. System modeling will take you two third of your time. It is worth the time to do systme modelling as thoroughly as you can. I believe all the novelty and contribution is in the systemlevel, not the circuit level. If you are doing single bit quantizer, circuit implement is not that hard.

3. After you done with system model. Try to implement it using Verilog-A for analog part and Verilog for digital part. Compare the simulation result with system level.

4. After you are confident with the result from step 3. you can synthize your verilog code and manually design the analog part of the circuit, do layout ....

5. At last, but not the least, if you really want to be an expert or make a living out of it. Study some non-linear feedback system theory. After all, every loop has A/D convertor is a non-linear feedback loop. Right now, we don't have analytical solutions for most of the delta-sigma modulator. That is why we heavily rely on the simulation.  

if You want to do good research on sigma delta adc, use matlab to analyse the advantages of using sigma delta compared to ordinary quantizer.then you can do it at spice level or some other tools like tanner.

_______________________________
To design Sigma_Delta Modulator ADC
:
1,understand the principle of SDM
2,determine the architecture of SDM according to the spec.
3,behavior modeling scale factor refering to the stablity.
4,behavior modeling the nonideal factor ,such as the cap noise vs. SNR,
slew rate and settling time of OTA vs.SNR and so on.
5,design circuit according to the model spec.
6,hspice simulation to verify function

_______________________________

To design Sigma Delta, firstly it is needed do design your order and transfer function. After that we need to verify whether ur system is stability or not. Then proceed a cicuit simualtion

Specsof a SDM ADC  adc are...

Resolution
In-band SNR
Maximum amplitude to the input
Out-of-band gain
Bandwidth

_____________________________
hello guys, i have a problem and need help.
i an design a sigma-delta modulator for digital audio application, BW=25KHz, the goal is to achieve snr=90dB. i used mash2-1 , and osr=128,Fs=6.4MHz.
i built the modulator in the hspice with ideal blocks, when the switch on resistance was 1ohm, the result was 104dB(the matlab result was 116dB),the second stage(first orser) snr was less than that in tha matlab, the low freq noise floor was much higher than that in the matlab. (1).is that the problem of the time in the two stage interface?
(2). when change the switch on resistance to 50ohm and 100ohm.., the snr dramatically drop to 65dB, and the low freq noise floor became much high and not shapped, but the opamp ouput showed that the settling was complete, and 50ohm is not big value in the application spec, have you met this problem before? hope you guys can give me some help, thanks a lot!
___________________________

Good Sigma-Delta AD textbook:

Regarding the books I've found useful (let's say practical) in this topic:

1. Rabii and Wooley book from Kluwer. Has interesting ideas about low voltage design, comparation of different OTAs for optimal power consumption, transistor sizings etc. Very good for circuit design. Unfortunately it is about single-bit quantizer.

2. Medeiro, Perez-Verdu & Rodriguez-Vazquez, "Top-down design of high performance sigma-delta modulators". Very good book about behavioural modelling of SDMs. Many ideas from here later appear in the Simulink models by people from Pavia Uni (Malcovati et al)

3. Li & Ismail, "Multi-standart CMOS wireless receivers: analyses and design" (Kluwer)

4. I've seen one PhD from Delft University dated 2003 or 2004, written by Romanian guy, can't recollect now more exact details, sorry.. It had good explanation about circuit-level design both for SC and CT blocks (his SDM conbines both of them)

5. PROGRAMMABLE, HIGH-DYNAMIC RANGE SIGMA-DELTA A/D CONVERTERS FOR
MULTISTANDARD, FULLY-INTEGRATED RF RECEIVERS, MS thesis from UC Berkeley by Kelvin Boo-Huat Khoo. Can be useful for a start. It is available in the web..
____________________
The paper given above is a very good one. The details of the paper is-----

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 50, NO. 3, MARCH 2003

Behavioral Modeling of Switched-Capacitor
Sigma–Delta Modulators
Piero Malcovati, Member, IEEE, Simona Brigati, Member, IEEE, Fabrizio Francesconi, Member, IEEE,
Franco Maloberti, Fellow, IEEE, Paolo Cusinato, and Andrea Baschirotto, Senior Member, IEEE

High-Speed, Low-Power Sigma-Delta Modulators for RF
Baseband Channel Applicationsby
Arnold R. Feldman
Doctor of Philosophy in Engineering-Electrical Engineering
and Computer Sciences
University of California, Berkeley
Professor Paul R. Gray, Chair

__________________________________
let me say what steps i followed to bring out the chip

First i took the required spec ,
mine was 0.35u CMOS 70Mhz continous time bandpass ADC .

There is basically a filter which is the major part of the design .. i took it as a 2nd order band pass filter.

First with all the design spec i simulated it in MATLAB with the transfer function of the FILTER..

once i got all the required graphs correct then i went to SPICE simulation...

THe filter which i am implemented in continous time could be implemented using Gm cell. (Lots of papers availabe in IEEE regarding implementaion)

once i got the same output graphs in SPICE i went to LAYOUT...
______________________________________